In recent years, with the development of semiconductor devices improved in multifunctionality and packaging density, a multilayer wiring structure in which a plurality of wiring layers are vertically stacked has found great use. In most cases of forming contacts used for connection of stacked wiring layers or the like, holes for wiring or contacts are formed in an interlayer dielectric film based on a design rule for the multilayer wiring structure, and conductive members or the like are embedded in the holes to form the contacts. In other cases, a film of a material used for wiring and for some other purpose is formed, and this wiring material film is etched to form the desired wiring.
Various patterns relating to such wiring layout have been designed from the viewpoint of efficiency, space saving and so on.
An example of a semiconductor device wiring structure such as a gate array type of structure for a general-purpose design will be described with reference to FIG. 13. In this structure, a wiring of a large width for stronger power supply, called a power supply ring (or a power ring) 40, exists outside a macrocell. Signal wiring, power supply wiring and ground wiring are placed in the macrocell inside the power supply ring 40. First wirings 41 in a lower layer and second wirings 42 in an upper layer perpendicular to each other are connected through vias 43. To increase the degree of design freedom with priority, this structure is designed so that the wirings 41 and 42 in the wiring layers are placed on a square grid uniform in each of X- and Y-directions (indicated by dotted lines in FIG. 13). That is, the wiring pitch and the via pitch can take the same minimum value.
If wirings and vias are placed on a square grid, the influence of a change in direction of the wirings on designing is small and a process check pattern can be formed without considering the direction of the wirings. Consequently, the number of kinds of process test element groups (TEGs) can be reduced, and TEGs can easily be prepared.
Another wiring structure has been proposed in which, in addition to a wiring grid having a first wiring and a second wiring respectively formed in X- and Y-directions as described above, third and fourth wirings are designed on an oblique wiring grid so as to form an angle of 45 degrees and another angle of 135 degrees from the X-direction. See, for example, Japanese Patent Laid-Open No. 2001-142931, Japanese Patent Laid-Open No. 2000-82743 and Japanese Patent-Laid-Open No. H9-148444.
In ordinary cases of forming the above-described wiring structures, holes are formed in an interlayer dielectric film and conductive members are embedded in the holes or a wiring material film is etched. A lithography technique is ordinarily used to form a resist mask which is used when the holes are formed or when the wiring material film is etched. However, with the recent tendency to make wiring patterns finer, various problems have arisen in lithography techniques. In some cases, the method for wiring design on a square grid (also called “uniform grid”) in particular cannot be used. As one reason for this, there is a resist receding (shrink) problem described below.
Generally speaking, if patterns become finer, the difference between a design size and the actual size of a resist pattern, called critical dimension shift (hereinafter referred to as “CD shift”), becomes larger.
FIG. 14 is a diagram showing a wiring width dependence of the CD shift in the lengthwise direction of a wiring. That is, FIG. 14 is a diagram showing the relationship between the width of a wiring (wiring width) and the CD shift in the lengthwise direction of the wiring. Here, the wiring is an isolated wiring.
As shown in FIG. 14, the CD shift tends to increase as the width of the isolated wiring is reduced. This is thought to be because the cut shape of the resist is degraded if the left opening area of the resist is reduced. For example, while the CD shift when the width of the isolated wiring is 0.4 μm is 0.02 μm, the CD shift when the width of the isolated wiring is 0.2 μm, is 0.06 μm. To reduce the influence of this CD shift on the transferred pattern configuration, a method (mask bias technique) for is known in which the amount of shrinking of the resist (CD shift) is estimated at the design stage, and the size of a mask (e.g., chromium mask) pattern is increased by an amount corresponding to the CD shift. For example, in a case where an isolated wiring having a width of 0.2 μm and a length of 700 μm is formed, a chromium mask having a length of 700.06 μm, which is the sum of 700 μm and the CD shift 0.06 μm shown in FIG. 14, is formed. Under exposure using this mask, the resist pattern after development is shrunk in the wiring lengthwise direction to have the same size (700 μm in length) as the design size. In FIG. 14, a region in which a design using a square grid is adaptable is hatched. If the mask bias technique is used by considering the CD shift in a case where the wiring width is smaller than 0.15 μm, wirings, which are placed with the minimum space set therebetween to avoid contact therebetween, contact each other. That is, a problem arises that a wiring design cannot be made on a square grid because the CD shift becomes larger than the wiring space margin.
Also, a method of adding a correction pattern to angular portions of a mask pattern in order to correct the CD shift due to a reduction of the angular portions of the resist pattern has been used.
As described above, it has been found that there is a problem with an application of the mask bias technique to wiring layout on a square grid when the width of isolated wirings is smaller than 0.15 μm. It is difficult to correct the CD shift with the mask bias technique or the method of adding a correction pattern when a finer pattern is used. That is, while the CD shift increases as the wiring width is reduced, the wiring space margin is reduced when a finer pattern having dense pattern lines is used, resulting in failure to form a CD-shift-corrected mask pattern. Consequently, it is difficult to make a correction by the mask bias technique.
With the multilayer wiring structure, there is also a problem that the process margin for vias becomes smaller relative to the process margin for wirings, and defects can occur easily in a via opening process. This is due to a low via data rate. FIG. 15 is a diagram showing a wiring length dependence of the data rate in a device region. The size of the device region is 17 μm×17 μm. A case in which wirings having a width of 0.1 μm and vias having a size of 0.1 μm×0.1 μm are placed with a minimum pitch of 200 nm in this device region will be described. When the wiring length of the first wirings or the second wirings is equal to a minimum length of 500 nm, the wiring data rate is about 27%. When the wiring length is equal to a device region limit of 17 μm, the wiring data rate is 50%. Thus, the wiring data rate is about 27 to 50%. On the other hand, as shown in FIG. 15 it is found that the via data rate is smaller by two orders of magnitude than the wiring data rate. Since the via data rate is low as described above, the light intensity in exposure at the time of via formation is weak and the optical contrast is reduced. If the diameter of the vias to be formed is small in such a state where the optical contrast is reduced, the depth of focus (DOF) is considerably reduced as shown in FIG. 16 and the via piercing characteristic degrades, resulting in a change in resist size. FIG. 16 is a diagram showing a via size dependence of the DOF. Also, if the etching process is designed by considering the density dependence of via etching, the isolated via piercing characteristic in particular degrades, resulting in a considerably large increase in the time required for etching including a loading effect. Thus, the amount of variation in the etching process with respect to variation in resist size is increased and it is not possible to form vias with high reproducibility.